1. Field of the Invention
The present invention relates to a printed circuit board design support program, a recording medium, a printed circuit board design support method, and a printed circuit board design support apparatus. In particular, the invention aims to appropriately arrange an interlayer connection member (a via hole, hereinafter, referred to as “via”) configured to electrically connect a plurality of conductive layers laminated on contact with an insulating layer.
2. Description of the Related Art
In recent years, in association with an increase in the speed of signals transmitted in an electronic device such as an information technology device, unnecessary electromagnetic waves (hereinafter, referred to as radiation noise) radiated from the electronic device cause a problem. In order to solve this problem, various designs for suppressing the radiation noise are carried out with respect to a wiring on a printed circuit board in the electronic device, a wire harness connected to the wiring, and a housing of the electronic device.
As a design method for suppressing the radiation noise, U.S. Pat. No. 6,937,480 and Japanese Patent Laid-Open No. 2007-272342 propose a technology for devising an arrangement of vias configured to electrically connect a plurality of conductive layers in the printed circuit board.
As to a design support apparatus for a printed-wiring assembly described in U.S. Pat. No. 6,937,480, a technology is disclosed with which the number of arranged vias in a predetermined range on the printed circuit board is calculated, and a situation is notified when the number of arranged vias is smaller than a predetermined number. Also, in this design support apparatus, a technology is disclosed for determining whether the vias are arranged at a predetermined interval and issuing a notification in a case where the vias are not arranged at the predetermined interval.
In a circuit board design support apparatus described in Japanese Patent Laid-Open No. 2007-272342, a location where a necessity for a layer change with respect to a return current route of a signal should be determined (hereinafter, referred to as check point) is detected. A technology is disclosed for displaying a synthesized area of an area in a range at a specified distance from the detected check point and an area where no vias are arranged.
As described above, in the printed-wiring assembly design support apparatus described in U.S. Pat. No. 6,937,480, a situation in which the number of arranged vias in the predetermined range is small or a situation in which the vias are not arranged at the predetermined distance is notified.
In addition, in the circuit board design support apparatus described in Japanese Patent Laid-Open No. 2007-272342, a synthesized area is calculated of an area in the vicinity of a location where the necessary for the layer change with respect to the return current route should be determined such as a layer change location of a signal line and an area where no power source or GND vias are arranged. Then, the necessity for the layer change with respect to the return current route is determined, and when the layer change with respect to the return current route is necessary, the synthesized area is visualized.
However, a user needs to visually determine whether a via can be added so as to satisfy a condition of USP or determine at which location the via can be added when the additional arrangement of the via is attempted to the synthesized area where the layer change with respect to the return current route is necessary in Japanese Patent Laid-Open No. 2007-272342. Therefore, it takes much time for the user to determine the location at which the via can be additionally arranged, and further, a mistake in the determination or an oversight of the position where the additional arrangement can be performed may occur.